1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device that includes a memory region and a logic circuit region. More particularly, the invention relates to a method for manufacturing a semiconductor device, where a non-volatile memory device formed in the memory region has two charge stored regions for one word gate.
2. Description of Related Art
Non-volatile semiconductor memory devices exist that are referred to as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type or a SONOS (Silicon Oxide Nitride Oxide Silicon) type in which a gate dielectric layer between a channel region and a control gate is formed from a stacked layered body of a silicon oxide layer and a silicon nitride layer, where a charge is trapped in the silicon nitride layer.
A MONOS type non-volatile memory device is shown in FIG. 20, and is disclosed in H. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-p.123.
The MONOS type memory cell 100 has a word gate 14 formed over a semiconductor substrate 10 through a first gate dielectric layer 12. Also, a first control gate 20 and a second control gate 30 in the form of sidewalls are disposed on both sides of the word gate 14. A second gate dielectric layer 22 is disposed between a bottom section of the first control gate 20 and the semiconductor substrate 10, and a dielectric layer 24 is disposed between a side surface of the first control gate 20 and the word gate 14. Similarly, a second gate dielectric layer 22 is disposed between a bottom section of the second control gate 30 and the semiconductor substrate 10, and a dielectric layer 24 is disposed between a side surface of the second control gate 30 and the word gate 14. Impurity layers 16 and 18 that each form a source region or a drain region are formed in the semiconductor substrate 10 between the opposing control gate 20 and the control gate 30 of adjacent memory cells.
In this manner, each memory cell 100 includes two MONOS type memory elements on side surfaces of the word gate 14. Also, these MONOS type memory elements are independently controlled. Therefore, a single memory cell 100 can store 2-bit information.
The following manufacturing method can be used to form a memory region including such a MONOS type memory cell and a logic circuit region including a peripheral circuit for the memory. Basically, memory cells in a memory region are formed, and then a peripheral circuit in a logic circuit region is formed. The memory region and the logic circuit region are formed, and then a variety of wiring layers are formed in upper layers above these regions through dielectric layers.
In the above manufacturing method, a dielectric layer, such as a silicon nitride layer, is formed, and then is polished by using a CMP (Chemical Mechanical Polishing) method.
The upper surface of the dielectric layer, after polishing, may preferably be flat in order to execute various steps to be conducted thereafter with high precision, for example, in order to form wirings and the like to be formed in upper layers above the dielectric layer with high precision. However, the polishing rates are not uniform. For example, the logic circuit region may be polished relatively quickly compared to the memory region, and there may be occasions where step differences may be created in the upper surface of the dielectric layer after polishing.
The present invention addresses or solves the above and/or other problems in the related art technique described above, and provides, in a step of polishing a dielectric layer in a method for manufacturing a semiconductor device that includes a memory region and a logic circuit region, a technique to achieve a better planarization of the dielectric layer upon polishing.
To address or solve at least a part of the problems described above, a first exemplary method for manufacturing a semiconductor device in accordance with the present invention pertains to a method for manufacturing a semiconductor device including a memory region that includes a non-volatile memory device and a logic circuit region that includes a peripheral circuit for the non-volatile memory device. The method includes:
preparing a semiconductor substrate having a conductive layer that is to become a word gate of the non-volatile semiconductor device;
forming a stopper layer above the conductive layer;
forming sidewall-like control gates on both side surfaces of the conductive layer through ONO films above a semiconductor layer of the memory region;
forming a gate electrode of a dielectric gate field effect transistor above the semiconductor layer of the logic circuit region;
forming a dielectric layer over an entire surface of the memory region and the logic circuit region of the semiconductor substrate;
forming a polishing restricting layer above a part of the dielectric layer; and
polishing the dielectric layer such that the stopper layer within the memory region is exposed, and the gate electrode within the logic circuit region is not exposed.
According to the manufacturing method described above, in the step of forming the polishing restricting layer, the polishing restricting layer can be formed above a region that is relatively quickly polished, for example, when the dielectric layer is polished. Consequently, step differences that may be created in the surface of the dielectric layer through polishing the dielectric layer can be reduced or suppressed, and the dielectric layer after polishing can be better planarized.
The step of forming the polishing restricting layer may preferably form the polishing restricting layer above the logic circuit region.
By so doing, when the dielectric layer above the logic circuit region is relatively quickly polished, the polishing in this region can be slowed down because the polishing restricting layer is formed above the region. Consequently, step differences that may be created in the surface of the dielectric layer can be reduced or suppressed, and the dielectric layer after polishing can be better planarized.
The polishing restricting layer can be formed with a silicon nitride or a metal.
Also, a second exemplary method for manufacturing a semiconductor device in accordance with the present invention pertains to a method for manufacturing a semiconductor device including a memory region that includes a non-volatile memory device and a logic circuit region that includes a peripheral circuit for the non-volatile memory device. The method includes:
forming a first dielectric layer above a semiconductor layer;
forming a first conductive layer above the first dielectric layer;
forming a stopper layer above the first conductive layer;
patterning the stopper layer and the first conductive layer in the memory region;
forming an ONO film over an entire surface of the memory region and the logic circuit region;
forming a second conductive layer above the ONO film;
anisotropically etching the second conductive layer to form sidewall-like control gates on both side surfaces of the first conductive layer through the ONO film at least within the memory region;
removing the stopper layer within the logic circuit region;
patterning the first conductive layer within the logic circuit region to form a gate electrode of a dielectric gate field effect transistor within the logic circuit region;
forming sidewall dielectric layers at least on both side surfaces of the gate electrode;
forming a first impurity layer that is to become a source region or a drain region of the non-volatile memory device and a second impurity layer that is to become a source region or a drain region of the dielectric gate field effect transistor;
forming a silicide layer on surfaces of the first impurity layer, the second impurity layer and the gate electrode;
forming a second dielectric layer over an entire surface of the memory region and the logic circuit region;
forming a polishing restricting layer over a part of the second dielectric layer;
polishing the second dielectric layer such that the stopper layer within the memory region is exposed, and the gate electrode within the logic circuit region is not exposed;
removing the stopper layer within the memory region; and
patterning the first conductive layer within the memory region to form a word gate of the non-volatile memory device within the memory region.
Also in the second method for manufacturing a semiconductor device, and similarly to the first method for manufacturing a semiconductor device, in the step of forming the polishing restricting layer, the polishing restricting layer can be formed above a region that is relatively quickly polished, for example, when the second dielectric layer is polished. Consequently, step differences that may be generated in the surface of the second dielectric layer through polishing the second dielectric layer can be reduced or suppressed, and the second dielectric layer after polishing can be planarized better.